1. Field of the Invention
This invention relates generally to ball grid array packages. More specifically, this invention relates to a method of using a single solder resist opening on a ball grid array substrate as both a saw fiducial and a pin one indicator.
2. State of the Art
Integrated circuits (ICs) are typically fabricated on a semiconductor wafer. To achieve the many semiconductor devices which may be formed thereon, the semiconductive wafer is subjected to deposition, etching, planarization and lithographic processes. The wafer is then cut or “diced” to form multiple semiconductor dice or semiconductor devices (IC chips). Typically, these individual semiconductor devices are transferred to a mounting substrate by an automatic “pick and place” process. Thereafter, a semiconductor device is electrically connected to the substrate and encapsulated by a molding apparatus into a final package. As trends continue toward higher performance, high input/output, and high board-manufacturing-yield, Ball Grid Array (BGA) packaging has become the technology of choice. In an ever increasing number of semiconductor applications, therefore, semiconductor devices or IC chips are mounted onto printed circuit boards or other mounting substrates which utilize BGA packaging methods.
Currently, some types of BGA packages, including fine pitch ball grid array (FPBGA) and micro ball grid array (μBGA) semiconductor device packages, are known in the art. The various types of BGA packages that have been developed include BGAs mounted on printed wiring boards, leadframes, and flexible tape. Presently, due to the need for smaller devices having a higher lead count and a smaller footprint, BGAs are used in chip scale packaging with increasing frequency.
One type of BGA package, known as “board-on-chip,” is shown in drawing FIGS. 1 and 2. A board-on-chip BGA package 1 typically comprises a substrate 10 having an upper or top surface 12, an opposing bottom surface 16, and an elongated aperture 15 extending through the middle thereof. Substrate 10 is typically a polymer laminate printed circuit board, although ceramics and other types of substrates may be used. During a die attach process, a semiconductor die 20 is mounted on the bottom surface 16 of the substrate 10 using an adhesive, adhesive and tape and/or adhesively coated tape, having active surface 22 of semiconductor die 20 upwardly facing and positioned below elongated aperture 15. Active surface 22 of semiconductor die 20 is configured having a plurality of bond pads 24 in single or multiple columns thereon which are substantially aligned with elongated aperture 15 as illustrated therein. As illustrated in drawing FIG. 1, bond pads 24 can be viewed through elongated aperture 15 as they are substantially aligned. Upper surface 12 of substrate 10 comprises a conductor surface wherein circuit traces 17 are formed, typically by etching, in a desired pattern. Alternatively, circuit traces 17 are formed on the semiconductor device side of substrate 10, or are formed internally within substrate 10. Circuit traces 17 are interconnected with a plurality of bond pads 18 and an array of contact pads 19 located along the periphery of elongated aperture 15 and extending from circuit traces 17, respectively. Bond pads 18 and contact pads 19 are generally located at separate terminal ends of circuit traces 17, as can be seen in drawing FIG. 1. Contact pads 19 are formed in arrays of varying numbers, dependent upon the specific application of the package. Each contact pad 19 typically comprises a solderable surface mount pad which is formed of a conductive metal, such as copper.
As shown in drawing FIG. 2, substrate 10 also includes a laminated or screen printed solder resist layer, or solder mask 40. Solder mask 40 is formed over top and bottom surfaces 12 and 16 and comprises an electrically insulating, low surface tension material which shields conductive members on top and bottom surfaces 12 and 16, respectively, from subsequent soldering and/or plating operations that might result in electrical shorts. The layer of solder resist comprising solder mask 40 initially may, if desired, cover all portions of surfaces 12 and 16 (including bond pads 18 and contact pads 19), with the exception of a semiconductor device receiving area of the substrate 10.
In a subsequent step, a pattern of via openings 42 is created in solder mask 40, via openings 42 corresponding to portions of bond pads 18 and contact pads 19 to which conductive elements, such as conductive wires 26 and solder balls 30, are respectively attached. To mask the areas over bond pads 18 and contact pads 19, solder mask 40 must obviously be deposited in a thickness at least minimally greater than the height of bond pads 18 and contact pads 19. Typically, the solder mask used to cover substrate 10 is a photoimageable material that can be blanket deposited as a wet or dry film. By using photolithographic processes, via openings 42 of predetermined diameters are formed by exposing and developing a desired pattern on the resist areas through a photoimaging mask, resulting in the removal of resist material and the exposure of bond pads 18 and contact pads 19.
Through a wire bonding process, conductive wires 26 extend from bond pads 24 of semiconductor die 20 through elogated aperture 15 to bond pads 18 located in the wirebonding area on terminal end portions of circuit traces 17 on or within substrate 10. Conductive wires 26 serve to electrically connect the bond pads 24 of semiconductor die 20 to bond pads 18 of substrate 10. In turn, bond pads 18 are electrically connected to contact pads 19 by circuit traces 17. Contact pads 19 are then placed in contact with respective electrically conductive, connective elements such as solder balls 30. Alternatively, solder balls 30 are placed directly upon, or in electrical communication with, the termination point of a selected circuit trace 17. Solder balls 30 may be filled with any suitable metal, such as gold, although other conductive metal-based solder balls or conductive filled epoxy materials are frequently used. As illustrated in drawing FIG. 2, conductive wires 26, die bond pads 24, and bond pads 18 are shown covered with a layer of protective encapsulant 25. Protective encapsulant layer 25 is also shown covering the inactive back side surface of semiconductor die 20 and bottom surface 16 of substrate 10.
Bond pad geometries are typically formed as a standard round shape. Because of the excellent self-centering property of solder ball interconnections, BGA applications have significantly greater misalignment tolerances than other interconnection techniques, such as quad flatpack leads. As such, relatively wide variations in solder ball placement are accommodated during reflow of the solder joints. Generally, the rule of thumb is that solder balls must have a radial placement accuracy wherein the solder is at least “half on pad.”
Generally, the types of bond pad layouts presently known in the art are Solder Mask Defined bond pad layouts and Non-Solder Mask Defined bond pad layouts. In Solder Mask Defined layouts of bond pads, the opening in the solder resist defining the solder ball mounting area is made smaller than the copper, or any suitable type metal, bond pad disposed underneath. Thus, the solder mask overlaps with the edge of the copper pad. This arrangement carries with it the advantage of providing better copper pad definition, since Solder Mask Defined layouts of bond pads are located by photoimaging, rather than by copper etching as is the case for Non-Solder Mask Defined pads.
In contrast, bond pads which are formed by Non-Solder Mask Defined layouts of bond pads have a solder mask opening which is larger than the copper pad, or any suitable type metal pad. In this situation, the size of the copper defines the size of the pad, and the size of the pad is determined by a copper etching process. Non-Solder Mask Defined layouts of bond pads are considered less accurate than those determined by solder mask photoimaging processes but offer advantages in that vision system registration of copper fiducials gives an exact location of the site so that any mis-registration error in regards to photoimaging the Solder Mask Defined layouts of pads will shift the location of the entire site relative to the vision fiducials.
Referring again to drawing FIGS. 1 and 2, to bond the solder balls to contact pads 19, flux is typically applied to contact pads 19 or to solder balls 30 and/or to both. Solder balls 30 are then placed in the via openings 42 over contact pads 19, and the solder is reflowed into a metallurgical solder bond. During the reflow process, the via opening 42 in solder mask 40 aid in positioning solder balls 30.
Contact pads 19 can be arranged in a grid array pattern wherein the conductive elements or solder balls 30 of a preselected size, or sizes, are spaced away from each other at one or more preselected distances, or pitches. Typically, solder ball sizes can be approximately 0.6 mm or less, and the solder balls may have a spacing, or pitch, of approximately 0.80 mm or less. When using tape substrates, high package densities with pitches approaching 0.05 mm are possible. In BGA arrangements using Plated Through-Hole (PTH) technology, consideration must be given to the placement of the bond pad. Bond pads which are placed too closely to a hole run the risk of solder melting and flowing into the hole, the wicking of the solder potentially creating a situation where the solder does not wet the entire bond pad, thus creating an “open” for that lead.
In packages using PFBGA or μBGA patterns, contact pads 19 are spaced at very small distances from each other, resulting in dimensionally small spacings or pitches for relatively small conductive elements, or solder balls 30, placed thereon.
Illustrated in drawing FIG. 3 is a top view of a portion of a BGA package 1 containing an unencapsulated BGA package 1, prior to singulation of BGA substrate 10. BGA substrate 10 is shown incorporating the use of a prior art alignment mark or fiducial 44 and a pin one indicator 46. Used for accurate automated assembly, alignment marks or fiducials 44 and pin one indicator 46 are typically incorporated on upper surface 12 of substrate 10. Alignment marks or fiducials 44, for example, ensure that substrate 10 is properly aligned and positioned for the automated mounting of a semiconductor die 20. As shown in drawing FIG. 3, marks for this purpose are generally found aligned with the lateral edges and the center axis of the substrate area in which semiconductor die 20 is to be attached. Alignment marks or fiducials 44, when set in “street lines,” may also be used for aligning a saw or other severing equipment to be used for the singulation or separation of BGA packages. Generally, alignment marks or fiducials 44 for the alignment of singulation or severing equipment are disposed on a peripheral area of substrate 10; the peripheral area is typically used as a clamping area during the encapsulation of semiconductor die 20 and its related interconnections within BGA package 1.
Pin one indicator 46 is used by automated die attach apparatus to orient semiconductor die 20 in the proper configuration. Pin one indicator 46 is generally positioned in close proximity to the semiconductor device mounting site in an area of the solder resist not occupied by bond pads 18, contact pads 19, or circuit traces 17.
Typically, pin one indicator 46 and alignment marks or fiducials 44 are formed as openings in the solder mask 40 (see drawing FIG. 2), allowing an underlying conductive feature (e.g., Cu, Au, Ni, etc.) to show through. Thus, the conductive feature showing through typically comprises the same metal as that of the conductors (i.e., bond pads 18, contact pads 19, and circuit traces 17) formed over the substrate surface. Methods for forming the pin one indicator 46 and alignment marks or fiducials 44 include exposure by photolithographic processes and the use of lasers. The shape of pin one indicators 46 and alignment marks or fiducials 44 are known to vary in the art. As shown in drawing FIG. 3, a standard design for a pin one indicator 46 is a triangularly shaped opening in the solder resist, while a standard design for an alignment mark or fiducial 44 is typically formed from openings in the solder resist fashioned as an X-Y axis.
Generally, automated die attachment apparatus use a vision system to locate a fiducial 44 and/or pin one indicator 46 on a substrate. By detecting the position of the fiducial 44 and pin one indicator 46, the position and orientation of substrate 10 can be accurately detected. Fiducials and pin one indicators (not shown), such as fiducials 44 and pin one indicators 46 on substrate 10, can also typically be found on semiconductor die 20 for orienting the semiconductor die 20 during the automated pick and place process. The vision system uses the semiconductor device fiducials and substrate fiducials 44 and pin one indicators 46 to check semiconductor die 20 position on the pickup tool and then drives the die attach apparatus ton adjust the die tool and substrate position for accurate semiconductor die 20 placement. A relatively simple system of vision recognition is the black and white digital recognition system (DRS). For a higher degree of sophistication in recognition, a pattern recognition system (PRS) can be used as a vision system.
Typically, the vision system reads the pin one indicator on the solder resist by scanning for contrasts and adjusting the backlighting to achieve the proper reflection. Using an X-Y table for proper alignment, the vision system checks the semiconductor die 20 position on the die pickup tool and directs the die machine to adjust the substrate and die tool into the correct positions, using X, Y, and θ (theta) directions, for precise semiconductor die 20 placement. Typically, semiconductor dice are presented to a bonding machine in wafers which may be mounted on tape on metal frames. For some die bonding machines, semiconductor dice may also be presented in gel or waffle packs. In the die bonding process, semiconductor dice are selectively picked from those of wafers respectively probe-tested in their manufacturing process using various testing equipment. Meanwhile, a mounting substrate has been indexed to the die attach site where a precise amount of adhesive, such as epoxy resin, is applied. The picked-up semiconductor device is then bonded to the die attach site of the mounting substrate via the adhesive. After the semiconductor die 20 has been adhesively mounted to the mounting substrate, a wire bonding process can take place.
Still referring to drawing FIG. 3, an accurate placement of semiconductor die 20 is critical for good wire bonding. Therefore, separate pin one indicators 46 and/or alignment marks or fiducials 44 must be used for each semiconductor die 20 in each multi-device bonding area on a substrate 10. For wire bonding, sophisticated vision systems are required to accurately and reliably position the vast numbers of wire bonds to be made in a package manufacturing operation. Furthermore, the accuracy of placement of a ball bond is particularly critical if using fine-pitch wire bonding technology. Therefore, PRS vision systems, in combination with alignment marks or fiducials 44, are typically used. During the wirebonding process, a substrate 10 is moved and indexed from bonding site to bonding site through a clamping apparatus which retains the substrate at sequential bonding sites for producing a plurality of wire-bonded semiconductor devices. In this process, guide holes 21 may be used for coarse alignment, while alignment marks or fiducials 44 are typically used to aid in precise alignment. In this process, the alignment marks or fiducials 44 may be formed separately from other alignment marks or fiducials which may be used for, e.g., die attach or saw singulation. Conductive wires 26 extending from bond pads 24 of the active surface 22 of a semiconductor die 20 are then bonded to bond pads 18 surrounding elongated aperture 15. Several choices may be made in the particular wire bonding process to be used. The selection of the proper wire bonding process is generally based on the pad pitch, device characteristics, and throughput requirements. Typically, either thermosonic ball bonding or ultrasonic wedge bonding is used. While thermosonic gold ball wire bonding is used for the majority of fine-pitch wire bonding, ultrasonic gold or aluminum wedge wire bonding is used for pad pitches below 60 μm.
Subsequent to wire bonding, semiconductor die 20 and its related electrical interconnections are subjected to a molding process where they are encapsulated to protect them from the outside environment. Typically, encapsulation entails positioning substrate 10 on a lower mold platen such that the portions to be encapsulated are in registration with multiple mold cavities formed in the lower mold platen. The mold is then closed when the upper platen, also containing a mold cavity, is lowered onto the lower platen. When the mold is closed, a peripheral portion of substrate 10, usually containing alignment marks or fudicials 44, is typically compressed between the upper and lower platens to seal the mold cavities in order to prevent leakage of liquified plastic molding compound. After wire bonding, individual or groups of packages are separated from one another by a cutting process, typically making use of alignment marks or fiducials 44 for the positioning of the singulation equipment to allow cutting along a package edge.
Several disadvantages are known in the art with regard to the use of conventional pin one indicators 46 and alignment marks or fiducials 44. First, while pin one indicators 46 and alignment marks or fiducials 44 are completely unnecessary for the operating characteristics of the completed BGA package, their presence disadvantageously takes up valuable real estate on substrate 10. This is problematic since the trend in industry today is towards smaller, yet denser packages. Foreseeably, higher density ball grid arrays will be used which will be populated so as to encroach on the package edge, resulting in smaller array pitches and tighter dimensional controls. For example, industry is increasingly moving towards widespread use of the “chip scale package,” in which the footprint of the package is only approximately twenty percent or less larger than that of the semiconductor device. Therefore, as BGA packages shrink and as density increases, it is desirable to make pin one indicators 46 and fiducials 44 as small as possible. Furthermore, large pin one indicator 46 and fiducial 44 openings in the solder resist can interfere with the operation of defect scanning vision systems. Finally, saw fiducials are typically placed in the encapsulation clamping areas where the non-planar solder resist surface that forms the fiducial can lead to resin bleed or flashing over the bond pads or contact pads during the molding process.
Accordingly, what is needed in the art are pin one indicators and fiducials which reduce the size of solder resist openings, thereby taking up a minimal amount of space and maintaining a substantially planar solder resist substrate surface.